1. How to choose PCB materials?
Choosing the right PCB material requires striking a balance between meeting design requirements, manufacturability, and cost. Design requirements encompass both electrical and mechanical aspects. Material selection is particularly important when designing very high-speed PCBs (frequencyes above GHz). For example, the commonly used FR-4 material may be unsuitable due to its high dielectric loss at frequencies of several GHz, which can significantly impact signal attenuation. Electrically, it’s crucial to consider whether the dielectric constant and dielectric loss are appropriate for the designed frequency.
2. How to avoid high-frequency interference?
The basic idea for avoiding high-frequency interference is to minimize the interference from the electromagnetic field of high-frequency signals, also known as crosstalk. This can be achieved by increasing the distance between high-speed signals and analog signals, or by adding ground guards/shunt traces near the analog signals. It’s also important to be aware of noise interference between digital ground and analog ground.
3. In high-speed design, how to solve the signal integrity problem?
Signal integrity is essentially an impedance matching issue. Factors affecting impedance matching include the signal source architecture and output impedance, the characteristic impedance of the traces, the characteristics of the load, and the topology of the traces. The solution lies in termination and adjusting the trace topology.
4. How is the differential distribution line method implemented?
There are two points to note when routing differential pairs: first, the lengths of the two lines should be as equal as possible; second, the spacing between the two lines (determined by the differential impedance) should remain constant, meaning they should be kept parallel. There are two ways to achieve parallelism: one is to run the two lines on the same routing layer (side-by-side), and the other is to run the two lines on adjacent layers (over-under). Generally, the former, side-by-side (parallel, side-by-side), is more commonly used.
5. How to implement differential routing for a clock signal line with only one output terminal?
Differential lines are only meaningful if both the signal source and the receiver are differential signals. Therefore, differential lines cannot be used for clock signals with only one output.
6. Can a matching resistor be added between the differential pairs at the receiving end?
Matching resistors are typically added between the differential pairs at the receiving end, and their value should be equal to the differential impedance. This will improve signal quality.
7. Why should the wiring of differential pairs be close together and parallel?
Differential pairs should be routed appropriately close together and parallel. Appropriate closeness is crucial because the spacing affects the differential impedance, a critical parameter in differential pair design. Parallelism is necessary to maintain consistent differential impedance. If the lines are inconsistently close, the differential impedance will be inconsistent, affecting signal integrity and timing delay.
8. How to handle theoretical conflicts in actual cabling?
Basically, separating the analog and digital grounds is correct. It’s important to note that signal traces should avoid crossing areas with separation (moat), and the returning current paths for power and signals should not be too large.
The crystal oscillator is an analog positive feedback oscillation circuit. To have a stable oscillation signal, it must meet the specifications of loop gain and phase. However, the oscillation specifications of this analog signal are easily affected by interference, and even adding ground guard traces may not completely isolate the interference. Moreover, if the distance is too great, noise on the ground plane will also affect the positive feedback oscillation circuit. Therefore, the crystal oscillator and the chip must be placed as close as possible.
Indeed, high-speed routing and EMI requirements often conflict. However, the basic principle is that resistors, capacitors, or ferrite beads added for EMI should not cause the electrical characteristics of the signal to deviate from specifications. Therefore, EMI issues should be addressed or reduced first by using routing and PCB layer stack-up techniques, such as routing high-speed signals on inner layers. Only then should resistors, capacitors, or ferrite beads be used to minimize damage to the signal.
9. How to resolve the contradiction between manual and automatic wiring for high-speed signals?
Most powerful routing software’s autorouters nowadays have constraints to control routing patterns and via counts. However, the capabilities of routing engines and the constraints offered by different EDA companies can vary significantly. For example, are there sufficient constraints to control the serpentine winding pattern, or the spacing between differential pairs? This affects whether the automatically generated routing matches the designer’s vision. Furthermore, the ease of manually adjusting routing is also related to the capabilities of the routing engine. For example, the pushing ability of traces, vias, and even the pushing ability of traces to copper pours. Therefore, choosing a router with a powerful routing engine is the best solution.
10. Regarding the test coupon.
A test coupon is used to measure the characteristic impedance of a manufactured PCB board using a Time Domain Reflectometer (TDR) to ensure it meets design requirements. Generally, the impedance to be controlled includes both single-line and differential pairs. Therefore, the trace width and spacing (for differential pairs) on the test coupon must match the traces to be controlled. Crucially, the location of the grounding point is critical. To minimize the inductance of the ground lead, the TDR probe is typically grounded very close to the probe tip. Therefore, the distance and method of the measurement point on the test coupon from the grounding point must be compatible with the probe used.
11. In high-speed PCB design, copper can be poured into the blank areas of signal layers, but how should the copper pours of multiple signal layers be allocated for grounding and power supply?
In general, copper pours in blank areas are mostly used for grounding. However, when pouring copper near high-speed signal lines, care should be taken to maintain the distance between the copper pour and the signal line, as the copper pour will slightly reduce the characteristic impedance of the trace. Also, care should be taken not to affect the characteristic impedance of other layers, such as in dual-strip line structures.
12. Can the characteristic impedance of a signal line on the power plane be calculated using a microstrip line model? Can the signal between the power and ground planes be calculated using a stripline model?
Yes, when calculating characteristic impedance, both the power plane and the ground plane must be considered as reference planes. For example, in a four-layer board: top layer – power layer – ground layer – bottom layer, the characteristic impedance model of the top layer trace is a microstrip line model with the power plane as the reference plane.
13. Can the test points automatically generated by software on a high-density printed circuit board generally meet the testing requirements of mass production?
Whether automatically generated test points by software meet testing requirements depends on whether the specifications for adding test points conform to the requirements of the testing equipment. Additionally, if the wiring is too dense and the specifications for adding test points are strict, it may not be possible to automatically add test points to every segment of the wire; in this case, manual addition of test points will be necessary.
14. Will adding test points affect the quality of high-speed signals?
Whether it will affect signal quality depends on the method of adding the test points and the signal speed. Basically, external test points (not using existing vias or DIP pins as test points) can be added to the line or a short section of wire can be pulled out from the line. The former is equivalent to adding a very small capacitor to the line, while the latter adds an extra branch. Both of these will have some impact on high-speed signals, the degree of which depends on the signal frequency and edge rate. The magnitude of the impact can be determined through simulation. In principle, smaller test points are better (while still meeting the requirements of the testing equipment), and shorter branches are better.
15. In a system composed of several PCBs, how should the ground wires be connected between the boards?
When signals or power are transmitted between interconnected PCBs, for example, if board A sends power or a signal to board B, an equal amount of current will flow back from the ground plane to board A (this is Kirchoff’s current law). This ground plane current will flow back through points of impedance. Therefore, at each interface where power or signals are interconnected, the number of pins allocated to the ground plane should not be too small to reduce impedance and thus reduce noise on the ground plane. Additionally, the entire current loop can be analyzed, especially the sections with higher current, and the ground plane or ground wire connections can be adjusted to control current flow (e.g., creating a low impedance at a certain point to allow most of the current to flow through that point), reducing the impact on other sensitive signals.
16. Could you recommend some technical books and data on high-speed PCB design?
Currently, high-speed digital circuits are used in fields such as communication networks and calculators. In communication networks, PCB boards are operating at frequencies around GHz, with up to 40 layers as far as I know. Calculator applications are also seeing advancements in chips, with operating frequencies reaching 400MHz (such as Rambus) and above on both PCs and servers. To meet these high-speed, high-density routing requirements, the demand for blind/buried vias, microvias, and build-up processes is increasing. These design requirements are readily available to manufacturers capable of mass production.
17. Two commonly referenced characteristic impedance formulas:
The microstrip line is defined as Z = {87/［sqrt（Er+1.41）］}ln［5.98H/（0.8W+T）］, where W is the line width, T is the copper thickness of the trace, H is the distance from the trace to the reference plane, and Er is the dielectric constant of the PCB material. This formula can only be applied when 0.1 ＜（W/H） ＜2.0 and 1 ＜（Er） ＜15.
The stripline is calculated as follows: Z = [60/sqrt(Er)]ln{4H/[0.67π(T+0.8W)]}, where H is the distance between the two reference planes, and the stripline is located between the two reference planes. This formula can only be applied when W/H < 0.35 and T/H < 0.25.
18. Can a ground wire be added in the middle of a differential signal line?
Generally, a ground wire should not be added in the middle of differential signals. This is because a key principle of differential signaling is to utilize the benefits of coupling between differential signals, such as flux cancellation and noise immunity. Adding a ground wire in the middle would disrupt the coupling effect.
19. Does the design of rigid-flex PCBs require specialized design software and specifications? Where in China can I find companies that can process this type of PCB?
Flexible printed circuit boards (FPCs) can be designed using standard PCB design software. They are then manufactured by FPC manufacturers using the same Gerber format. Due to differences in manufacturing processes compared to standard PCBs, each manufacturer will have specific requirements regarding trace width, trace spacing, and via diameter, depending on their manufacturing capabilities. Additionally, copper foil can be added at the bends of the flexible circuit board for reinforcement. Manufacturers can be found online by searching for “FPC” as a keyword.
20. What are the principles for appropriately selecting the grounding points of the PCB and the casing?
The principle for selecting the PCB and chassis grounding point is to utilize the chassis ground to provide a low-impedance path for the returning current and to control this returning current. For example, near high-frequency devices or clock generators, the PCB ground plane can be connected to the chassis ground using fixing screws to minimize the overall current loop area, thereby reducing electromagnetic radiation.
21. What aspects should be considered when debugging a circuit board?
For digital circuits, the first three things to confirm in sequence are: 1. Confirm that all power supply values meet design requirements. Some systems with multiple power supplies may require specific rules regarding the order and speed of power supply activation. 2. Confirm that all clock signal frequencies are functioning correctly and that there are no non-monotonic issues at signal edges. 3. Confirm that the reset signal meets specifications. If all of these are normal, the chip should emit a cycle of signals. Next, debug according to the system’s operating principles and bus protocol.
22. When the circuit board size is fixed, if the design needs to accommodate more functions, it is often necessary to increase the trace density of the PCB. However, this may lead to increased mutual interference between traces. At the same time, if the traces are too thin, the impedance cannot be reduced. Please introduce the techniques for high-speed (>100MHz) high-density PCB design.
When designing high-speed, high-density PCBs, crosstalk interference requires special attention because it significantly impacts timing and signal integrity. Here are a few points to consider:
Control the continuity and matching of the characteristic impedance of the traces.
The size of the trace spacing. A commonly seen spacing is twice the trace width. Simulations can be used to understand the impact of trace spacing on timing and signal integrity, and to determine the tolerable spacing. Results may vary depending on the specific chip.
Choose the appropriate termination method.
Avoid routing cables in the same direction on adjacent floors, or even having cables that overlap vertically, as this type of crosstalk is greater than that of adjacent cables on the same floor.
Blind/buried vias can be used to increase trace area. However, this increases the manufacturing cost of the PCB board. Achieving perfect parallelism and equal length is indeed difficult in practice, but it should still be done as best as possible.
In addition, differential and common-mode terminations can be reserved to mitigate the impact on timing and signal integrity.
23. LC circuits are often used for filtering in analog power supplies. But why is it that sometimes LC filters are less effective than RC filters?
Comparing the filtering effects of LC and RC filters requires considering the appropriateness of the frequency band to be filtered out and the choice of inductance value. This is because the inductive reactance of an inductor is related to both its value and frequency. If the power supply noise frequency is low and the inductance value is insufficient, the filtering effect may be worse than RC. However, the trade-off for using RC filtering is that the resistor itself consumes energy, resulting in lower efficiency, and the power handling capacity of the selected resistor must be carefully considered.
24. What are the methods for selecting inductor and capacitor values when filtering?
When selecting the inductor value, in addition to considering the noise frequency to be filtered out, the responsiveness to instantaneous current must also be taken into account. If the output of the LC circuit may require a large instantaneous current, an inductor value that is too large will impede the speed at which this large current flows through the inductor, increasing ripple noise. The capacitor value is related to the tolerance ripple noise specification. The lower the ripple noise requirement, the larger the capacitor value should be. The ESR/ESL of the capacitor will also have an impact. Furthermore, if this LC circuit is placed at the output of a switching regulation power supply, attention must be paid to the impact of the poles and zeros generated by this LC circuit on the stability of the negative feedback control loop.
25. How to meet EMC requirements as much as possible without creating too much cost pressure?
The increased cost of PCBs due to EMC issues is usually due to increasing the number of ground planes to enhance shielding and adding high-frequency harmonic suppression devices such as ferrite beads and chokes. In addition, other shielding structures are usually required to ensure the entire system meets EMC requirements. The following are some PCB design techniques to reduce electromagnetic radiation generated by circuits.
Choose devices with a slower slew rate whenever possible to reduce the high-frequency components generated by the signal.
Pay attention to the placement of high-frequency components; do not place them too close to external connectors.
Pay attention to impedance matching for high-speed signals, routing layers, and their return current paths to reduce high-frequency reflections and radiation.
Place sufficient and appropriate decoupling capacitors on the power pins of each device to mitigate noise on the power and ground planes. Pay special attention to whether the frequency response and temperature characteristics of the capacitors meet the design requirements.
The ground near the external connector can be appropriately separated from the ground layer, and the ground of the connector should be connected to the chassis ground as close as possible.
Ground guard/shunt traces can be appropriately used near particularly high-speed signals. However, attention should be paid to the impact of guard/shunt traces on the characteristic impedance of the traces.
The power layer is recessed 20H from the ground layer, where H is the distance between the power layer and the ground layer.
26. When there are multiple digital/analog functional blocks on a PCB board, the conventional practice is to separate the digital and analog grounds. Why is that?
The reason for separating digital and analog grounds is that digital circuits generate noise on both power and ground when switching between high and low potentials. The magnitude of this noise depends on the signal speed and current magnitude. If the ground plane is not separated and the noise generated by the digital circuitry is significant while the analog circuitry is very close together, the analog signal will still be interfered with by ground noise even if the digital and analog signals do not cross. In other words, the method of not separating digital and analog grounds can only be used when the analog circuitry is far from the digital circuitry that generates significant noise.
27. Another approach is to ensure that the digital and analog signals are laid out separately and do not cross each other, without dividing the ground plane of the entire PCB board; both the digital and analog grounds are connected to the same ground plane. What is the rationale behind this?
The requirement that digital and analog signal traces cannot cross is because the return current path of a slightly faster digital signal will try to flow back to the source of the digital signal along the ground near the bottom of the trace. If the digital and analog signal traces cross, the noise generated by the return current will appear in the analog circuit area.
28. How to consider impedance matching issues when designing a high-speed PCB schematic?
Impedance matching is a crucial element in designing high-speed PCB circuits. Impedance values are influenced by routing methods, such as whether the trace is on a surface layer (microstrip) or an inner layer (stripline/double stripline), the distance from the reference layer (power or ground), trace width, and PCB material. These factors all affect the characteristic impedance of the trace. In other words, the impedance value can only be determined after routing. Simulation software, due to limitations in the circuit model or the mathematical algorithms used, often cannot account for impedance discontinuities. In such cases, the schematic can only provide some terminators, such as series resistors, to mitigate the effects of impedance discontinuities. However, the fundamental solution is to avoid impedance discontinuities during the routing process itself.
29. Where can I find a relatively accurate IBIS model library?
The accuracy of the IBIS model directly affects the simulation results. Essentially, IBIS can be seen as the electrical characteristic data of the equivalent circuit of the actual chip’s I/O buffer. It can generally be obtained by converting a SPICE model (measurement is also possible, but more commonly used). However, SPICE data is related to chip manufacturing, so the SPICE data for the same device will differ between different chip manufacturers, and consequently, the data in the converted IBIS model will also vary. In other words, if using a device from manufacturer A, only they can provide accurate model data for their device, because no one else knows better than them what manufacturing process their device uses. If the IBIS provided by the manufacturer is inaccurate, the only fundamental solution is to continuously request improvements from that manufacturer.
30. When designing high-speed PCBs, what aspects should designers consider regarding EMC and EMI rules?
Generally, EMI/EMC design requires consideration of both radiated and conducted frequencies. The former pertains to higher frequencies (>30MHz), while the latter pertains to lower frequencies (<30MHz). Therefore, it’s crucial not to focus solely on high frequencies while neglecting lower frequencies. A good EMI/EMC design must consider component placement, PCB stack-up arrangement, routing of critical connections, and component selection from the initial layout stage. Failure to plan these aspects beforehand will lead to inefficient and costly post-design solutions. For example, clock generators should be placed away from external connectors; high-speed signals should be routed on inner layers with attention to impedance matching and reference layer continuity to minimize reflections; the slew rate of signals driven by components should be minimized to reduce high-frequency components; and decoupling/bypass capacitors should be selected based on their frequency response to reduce power plane noise. Furthermore, the return path of high-frequency signal currents should be designed to minimize loop area (i.e., minimize loop impedance) to reduce radiation. Ground plane segmentation can also be used to control the range of high-frequency noise. Choose appropriate chassis grounding points for the PCB and the casing.
31. How to choose an EDA tool?
Thermal analysis is not a strong feature in current PCB design software, so it is not recommended. For other functions, PADS or Cadence offer good performance-price ratios. Beginners in PLD design can use the integrated environment provided by the PLD chip manufacturer. For designs involving millions of gates or more, single-point tools can be used.
32. Please recommend an EDA software suitable for high-speed signal processing and transmission.
For conventional circuit design, Innovda’s PADS is excellent, and it comes with matching simulation software; this type of design often accounts for 70% of applications. For high-speed circuit design, and mixed-signal circuits, Cadence’s solutions offer a good balance of performance and price. Of course, Mentor’s performance is also very good, especially its design flow management.
33. Explanation of the meaning of each layer on a PCB board
Topoverlay —- The name of the top-level component, also called the top silkscreen or top component legend, such as R1 C5.
IC10.bottomoverlay—-Similarly, multilayer—–If you design a 4-layer board and place a free pad or via, defining it as a multilayer, then its pad will automatically appear on all 4 layers. If you only define it as the top layer, then its pad will only appear on the top layer.
34. For high-frequency PCB design above 2G, what aspects should be paid special attention to in terms of routing and layout?
High-frequency PCBs above 2GHz fall under the category of radio frequency (RF) circuit design and are not within the scope of high-speed digital circuit design. RF circuit layout and routing should be considered in conjunction with the schematic, as both can cause distribution effects. Furthermore, some passive components in RF circuit design are implemented using parametric definitions and specially shaped copper foils, thus requiring EDA tools to provide parametric components and the ability to edit specially shaped copper foils. Mentor’s BoardStation has a dedicated RF design module that meets these requirements. Additionally, RF design generally requires specialized RF circuit analysis tools; Agilent’s EESoft is a leading example in the industry, and it has a good interface with Mentor’s tools.
35. For high-frequency PCB designs above 2GHz, what rules should be followed in the design of microstrip circuits?
RF microstrip line design requires the use of 3D field analysis tools to extract transmission line parameters. All rules should be specified within this field extraction tool.
36. For a PCB with all-digital signals, there is an 80MHz clock source on the board. Besides using silkscreen (grounded), what kind of protection circuit should be used to ensure sufficient drive capability?
Ensuring clock drive capability should not be achieved through protection mechanisms; a clock driver chip is typically used. Concerns about clock drive capability usually arise from multiple clock loads. Using a clock driver chip, a single clock signal is multiplied into several signals connected point-to-point. When selecting a driver chip, besides ensuring basic matching with the load and meeting signal edge requirements (typically, clock signals are edge-sensitive), the clock delay within the driver chip must be factored into system timing calculations.
37. If a separate clock signal board is used, what kind of interface is typically used to ensure that the transmission of the clock signal is minimally affected?
The shorter the clock signal, the smaller the transmission line effect. Using a separate clock signal board will increase the signal wiring length. Furthermore, grounding and power supply for the board are also issues. For long-distance transmission, differential signals are recommended. The L-type signal can meet the drive capability requirements, but since your clock isn’t very fast, it’s unnecessary.
38 and 27MHz are SDRAM clock lines (80MHz-90MHz). The second and third harmonics of these clock lines are located in the VHF band, causing significant interference when they enter at high frequencies from the receiver. Besides shortening the line length, what other good solutions are there?
If the third harmonic is high and the second harmonic is low, it might be because the signal duty cycle is 50%, as there are no even-order harmonics in this case. In this case, the signal duty cycle needs to be adjusted. Furthermore, for unidirectional clock signals, source-end series matching is generally used. This suppresses secondary reflections without affecting the clock edge rate. The source-end matching value can be obtained using the formula shown in the following figure.
39. What is the topology of cabling?
Topology, sometimes also called routing order, refers to the cabling sequence of a multi-port network.
40. How to adjust the topology of the wiring to improve signal integrity?
The signal direction in this type of network is quite complex because the topology has different effects on unidirectional, bidirectional, and different signal levels, making it difficult to say which topology is beneficial to signal quality. Moreover, choosing the right topology for pre-simulation places high demands on engineers, requiring them to understand circuit principles, signal types, and even wiring complexity.
41. How can EMI problems be reduced by arranging the stack-up?
First, EMI must be considered from a system perspective; PCB design alone cannot solve the problem. Regarding EMI, I believe the main benefits of layer stack-up are providing short return paths for signals, reducing coupling area, and suppressing differential-mode interference. Additionally, tight coupling between the ground and power layers, and appropriately extending the power layer beyond its outer edge, is beneficial for suppressing common-mode interference.
42. Why is copper plating necessary?
There are several reasons for copper pouring. 1. EMC: Large areas of ground or power copper pouring provide shielding. Some special grounds, such as PGND, also provide protection. 2. PCB manufacturing requirements: Copper pouring is generally used on PCB layers with fewer traces to ensure plating quality or prevent lamination deformation. 3. Signal integrity requirements: It provides a complete return path for high-frequency digital signals and reduces DC network traces. Other reasons include heat dissipation and the mounting requirements of special components.
43. In a system that includes DSPs and PLDs, what issues should be considered when wiring?
Consider the ratio of your signal rate to wiring length. If the signal delay on the transmission line is comparable to the signal transition time, then signal integrity should be considered. Additionally, for multiple DSPs, the routing topology of clock and data signals will also affect signal quality and timing, which needs to be monitored.
44. Besides Protel, are there any other good tools for routing?
As for tools, besides PROTEL, there are many other cabling tools, such as MENTOR’s WG2000, EN2000 series and PowerPCB, Cadence’s Allegro, Zuken’s Cadstar, CR5000, etc., each with its own strengths.
45. What is a “signal return path”?
The signal return path, or return current, is the path from the driver along the PCB transmission line to the load, and then from the load back to the driver via a short path along ground or power. This return signal on ground or power is called the signal return path. Dr. Johnson explains in his book that high-frequency signal transmission is actually a process of charging the dielectric capacitance sandwiched between the transmission line and the DC layer. Signal processing (SI) analyzes the electromagnetic properties of this field and the coupling between them.
46. How to connect to plugins for SI analysis?
The IBIS 3.2 specification describes connector models. EBD models are generally used. For special boards, such as backplanes, SPICE models are required. Multi-board simulation software (HYPERLYNX or IS_multiboard) can also be used. When building a multi-board system, the connector distribution parameters are input, usually obtained from the connector manual. This method is not ideal, but it’s acceptable as long as it’s within acceptable limits.
47. What are the different termination methods?
Termination, also known as matching, is generally classified into active matching and terminating matching based on the matching location. Active matching typically involves a series resistor, while terminating matching typically involves a parallel resistor. There are various methods, including pull-up resistors, pull-down resistors, Thevenin matching, AC matching, and Schottky diode matching.
48. What factors determine the use of termination (matching) method?
The matching method is generally determined by the BUFFER characteristics, topology, level type, and decision method, and the signal duty cycle and system power consumption should also be considered.
49. What are the rules for using termination (matching) methods?
Timing is crucial in digital circuits, and matching aims to improve signal quality, ensuring a definite signal at the decision point. For level-active signals, signal quality is stable while maintaining setup and hold times; for delay-active signals, the signal change rate meets requirements while maintaining signal delay monotonicity. Mentor ICX product training materials contain some information on matching. Additionally, “High Speed Digital Design: A Handbook of Blackmagic” has a chapter specifically on terminals, explaining the role of matching in signal integrity from the perspective of electromagnetic wave principles, which can be used as a reference.
50. Can the logic function of a device be simulated using its IBIS model? If not, how can board-level and system-level simulations of the circuit be performed?
The IBIS model is a behavioral-level model and cannot be used for functional simulation. Functional simulation requires the use of the SPICE model or other structural-level models.
51. In systems where digital and analog circuits coexist, there are two approaches: one is to separate the digital ground and analog ground, for example, in the ground plane, where the digital ground is a separate block and the analog ground is a separate block, connected at individual points using copper foil or FB ferrite beads, while the power supplies are not separated; the other is to separate the analog power supply and digital power supply using FB ferrite beads, while the ground is a unified ground. Mr. Li, are these two methods equally effective?
In principle, they are the same. This is because power supply and ground are equivalent for high-frequency signals.
The purpose of separating analog and digital sections is to mitigate interference, primarily from digital circuits interfering with analog circuits. However, this separation can lead to incomplete signal return paths, affecting the signal quality of digital signals and impacting system EMC. Therefore, regardless of which plane is separated, it’s crucial to assess whether this increases the signal return path and the extent of interference between the return signal and normal operating signals. Some hybrid designs now also avoid separating power and ground, instead using separate layouts for digital and analog sections to prevent cross-section signals.
52. Safety regulations: What are the specific meanings of FCC and EMC?
FCC: Federal Communications Commission (United States Communications Commission)
EMC: Electromagnetic Compatibility
The FCC is a standards organization, and EMC is a standard. Standards are issued for specific reasons, and each standard and its testing methods are designed to meet those reasons.
53. What is the difference distribution line?
Differential signals, sometimes called differential signals, use two identical signals with opposite polarities to transmit one data stream, relying on the difference in signal levels to make a decision. To ensure that the two signals are completely identical, they must be kept parallel during wiring, and the line width and spacing must remain constant.
54. What PCB simulation software is available?
There are many types of simulations. Commonly used software for high-speed digital circuit signal integrity analysis (SI) simulations includes ICX, SignalVision, HyperlynX, XTK, and SpecialQuest. Hspice is also sometimes used.
55. How does PCB simulation software perform layout simulation?
In high-speed digital circuits, in order to improve signal quality and reduce wiring difficulty, multi-layer boards are generally used, with dedicated power and ground layers.
56. How can we ensure the stability of signals above 50 Mbps during layout and wiring?
The key to high-speed digital signal cabling is minimizing the impact of transmission lines on signal quality. Therefore, for high-speed signals above 100 Mbps, signal traces should be kept as short as possible. In digital circuits, high-speed signals are defined by their rise time. Furthermore, different types of signals (such as TTL, GTL, and LVTTL) require different methods to ensure signal quality.
57. The radio frequency (RF) section, intermediate frequency (IF) section, and even the low-frequency circuitry for monitoring the outdoor unit are often deployed on the same PCB. What are the material requirements for such a PCB? How can interference between the RF, IF, and low-frequency circuits be prevented?
Hybrid circuit design is a significant challenge. A perfect solution is difficult to find.
In general, RF circuits are laid out and routed as an independent single board in a system, and may even have dedicated shielding cavities. Furthermore, RF circuits are typically single-sided or double-sided boards, with relatively simple circuitry. All of these measures aim to minimize the impact on the distributed parameters of the RF circuits and improve the consistency of the RF system. Compared to standard FR4 material, RF circuit boards tend to use high-Q substrates. These materials have a lower dielectric constant, lower transmission line capacitance, higher impedance, and lower signal transmission delay. In hybrid circuit designs, although RF and digital circuits are placed on the same PCB, they are generally separated into RF circuit areas and digital circuit areas, with separate layouts and routing. These are shielded using grounding vias and shielding boxes.
58. For the RF section, the intermediate frequency section and the low frequency circuit section are deployed on the same PCB. What solutions does Mentor have?
Mentor’s board-level system design software, in addition to basic circuit design functions, also includes a dedicated RF design module. The RF schematic design module provides parametric device models and a bidirectional interface with RF circuit analysis and simulation tools such as EESOFT. The RF layout module offers pattern editing functions specifically for RF circuit placement and routing, and also has a bidirectional interface with RF circuit analysis and simulation tools like EESOFT. The results of analysis and simulation can be back-annotated to the schematic and PCB. Furthermore, Mentor software’s design management functions facilitate design reuse, design derivation, and collaborative design, significantly accelerating the hybrid circuit design process. Mobile phone boards are typical examples of hybrid circuit designs, and many large mobile phone manufacturers use Mentor combined with Agilent’s EESOFT as their design platform.
59. What is Mentor’s product structure?
Mentor Graphics’ PCB tools include the WG (formerly Veribest) series and the Enterprise (Boardstation) series.
60. How does Mentor’s PCB design software support BGA, PGA, COB, and other packages?
Mentor’s Autoactive Router, developed from the acquired VeriBest, is the industry’s first meshless, arbitrary-angle router. As is well known, for ball grid arrays and COB devices, meshless, arbitrary-angle routers are key to improving routing throughput. The new Autoactive Router adds features such as push-via, copper foil, and REROUTE, making it more convenient to use. Furthermore, it supports high-speed routing, including routing of signals with time delay requirements and differential pair routing.
61. How does Mentor’s PCB design software handle differential lines?
After defining the differential pair attributes, the Mentor software allows two differential pairs to be routed together, strictly ensuring the difference in differential pair line width, spacing, and length. It can automatically separate when encountering obstacles, and via methods can be selected when changing layers.
62. On a 12-layer PCB, there are three power layers: 2.2V, 3.3V, and 5V. If each power layer is placed on a separate layer, how should the ground be handled?
Generally speaking, placing the three power supplies on three separate layers provides better signal quality because it reduces the likelihood of signal splitting across planes. Segmentation is a critical factor affecting signal quality, but simulation software typically ignores it. For power and ground layers, they are equivalent for high-frequency signals. In practice, besides signal quality, factors such as power plane coupling (using adjacent ground planes to reduce AC impedance) and layer stack symmetry must be considered.
63. How is it checked whether a PCB meets the design process requirements before it leaves the factory?
Many PCB manufacturers conduct power-on network continuity tests on finished PCBs before they leave the factory to ensure all connections are correct. Meanwhile, an increasing number of manufacturers are also using X-ray testing to check for faults during etching or lamination. For finished boards after surface mount technology (SMT) assembly, ICT testing is generally used, which requires adding ICT test points during PCB design. If problems are found, a special X-ray inspection device can also be used to rule out manufacturing defects as the cause of the fault.
64. Is “mechanical protection” the same as the protection of the casing?
Yes. The casing should be as airtight as possible, using minimal or no conductive materials, and grounded whenever possible.
65. When selecting a chip, should the chip’s ESD performance also be considered?
Whether using a double-layer or multi-layer board, the ground plane area should be maximized. When selecting chips, their ESD characteristics must be considered; these are usually mentioned in the chip’s specifications, and even the performance of the same chip from different manufacturers can vary. Paying close attention to these aspects during the design process and considering all factors will ensure a certain level of performance for the resulting circuit board. However, ESD issues can still occur, therefore, structural protection is also crucial for ESD protection.
66. When making a PCB, should the ground wire be in a closed configuration to reduce interference?
When making PCB boards, it is generally necessary to reduce the loop area in order to reduce interference. When routing ground lines, it is better to route them in a tree-like pattern rather than in a closed loop. Also, the ground area should be maximized as much as possible.
67. If the emulator uses one power supply and the PCB board uses another power supply, should the grounds of these two power supplies be connected together?
Using separate power supplies would be ideal, as this reduces the likelihood of interference between them; however, most devices have specific requirements. Since the emulator and the PCB board use two separate power supplies, in my opinion, they shouldn’t share a common ground.
68. If a circuit is composed of several PCB boards, should they share a common ground?
A circuit consisting of several PCBs usually requires a common ground, as using multiple power supplies in a single circuit is impractical. However, if you have specific requirements, you can use different power supplies, which will reduce interference.
69. Design a handheld product with an LCD and a metal casing. During ESD testing, it fails the ICE-1000-4-2 test; the contact voltage is only 1100V, while the air voltage is 6000V. During ESD coupling testing, it can only pass 3000V horizontally and 4000V vertically. The CPU frequency is 33MHz. What methods can be used to pass the ESD test?
Handheld products with metal casings are more susceptible to ESD issues, and the LCD is likely to experience more malfunctions. If the existing metal material cannot be changed, it is recommended to add anti-static materials inside the mechanism, strengthen the PCB ground, and find a way to ground the LCD. Of course, the specific implementation depends on the specific circumstances.
70. When designing a system containing DSP and PLD, what aspects should be considered regarding ESD?
For general systems, the primary focus should be on protecting the parts that come into direct contact with the human body, implementing appropriate protection in both the circuitry and the structure. The extent of ESD’s impact on the system depends on the specific circumstances. ESD phenomena are more severe in dry environments, and the effects are more pronounced in more sensitive and delicate systems. While the impact of ESD may not always be significant in large systems, careful consideration during the design phase is still essential to prevent potential problems.
发表评论